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RT8223P 1 ds8223p-01 june 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. high efficiency, main power supply controller for notebook computer general description the RT8223P is a dual step-down, switch-mode power supply controller generating logic-supply voltages in battery-powered systems. it includes two pulse width modulation (pwm) controllers adjustable from 2v to 5.5v, and also features fixed 5v/3.3v linear regulators. each linear regulator provides up to 100ma output current with automatic linear regulator bootstrapping to the pwm outputs. the RT8223P includes on-board power up sequencing, a power good output, internal soft-start, and soft-discharge output that prevents negative voltage during shutdown. the constant on-time pwm scheme can operate without sense resistors and provide 100ns load transient response while maintaining nearly constant switching frequency. to eliminate noise in audio applications, an ultrasonic mode is included, which maintains the switching frequency above 25khz. moreover, the diode-emulation mode maximizes efficiency for light load applications. the RT8223P is available in a wqfn-24l 4x4 package. features z z z z z constant on-time control with 100ns load step response z z z z z wide input voltage range : 6v to 25v z z z z z dual adjustable outputs from 2v to 5.5v z z z z z fixed 3.3v and 5v ldo output : 100ma z z z z z 2v reference voltage z z z z z frequency selectable via tonsel setting z z z z z 4700ppm/ c r ds(on) current sensing z z z z z programmable current limit combined with enable control z z z z z selectable pwm, dem, or ultrasonic mode z z z z z internal soft-start and soft-discharge z z z z z high efficiency up to 97% z z z z z 5mw quiescent power dissipation z z z z z thermal shutdown z z z z z rohs compliant and halogen free applications z notebook and sub-notebook computers z 3-cell and 4-cell li+ battery-powered devices marking information 20 : product code ymdnn : date code pin configurations (top view) wqfn-24l 4x4 entrip1 fb1 ref tonsel fb2 entrip2 lgate2 vout2 vreg3 boot2 phase2 ugate2 enc vreg5 gnd skipsel en vin ugate1 lgate1 vout1 pgood boot1 phase1 gnd 1 2 3 4 5 6 78910 12 11 18 17 16 15 14 13 21 20 19 24 22 23 25 20 ym dnn package type qw : wqfn-24l 4x4 (w-type) lead plating system z : eco (ecological element with halogen free and pb free) RT8223P
RT8223P 2 ds8223p-01 june 2011 www.richtek.com functional pin description pin no. pin name pin function 1 entrip1 channel 1 enable and current limit setting input. connect a resistor to gnd to set the threshold for channel 1 synchronous r ds(on) sense. the gnd ? phase1 current limit threshold is 1/10th the voltage seen at entrip1 over a 0.515v to 3v range. there is an internal 10 a current source from vreg5 to entrip1. leave entrip1 floating or short entrip1 to gnd to shut down channel 1. 2 fb1 smps1 feedback input. connect fb1 to a resistive voltage divider from vout1 to gnd to adjust output from 2v to 5.5v. 3 ref 2v reference output. bypass to gnd with a minimum 0.22 f capacitor. ref can source up to 100 a for external loads. loading ref degrades fbx and output accuracy according to the ref load-regulation error. 4 tonsel frequency selectable input for vout1/vout2 respectively. 400khz/500khz : connect to vreg5 or vreg3 300khz/375khz : connect to ref 200khz/250khz : connect to gnd 5 fb2 smps2 feedback input. connect fb2 to a resistive voltage divider from vout2 to gnd to adjust output voltage from 2v to 5.5v. 6 entrip2 channel 2 enable and current limit setting input. connect a resistor to gnd to set the threshold for channel 2 synchronous r ds(on) sense. the gnd ? phase2 current limit threshold is 1/10th the voltage seen at entrip2 over a 0.515v to 3v range. there is an internal 10 a current source from vreg5 to entrip2. leave entrip2 floating or short entrip2 to gnd to shut down channel 2. 7 vout2 bypass pin for smps2. connect to the smps2 output to bypass efficient power for vreg3 pin. vout2 is also for the smps2 output soft-discharge. 8 vreg3 3.3v linear regulator output. to be continued typical application circuit v o u t 1 5 v 0 . 1 f RT8223P phase1 lgate1 boot1 ugate1 vout1 vin vreg5 vreg3 pgood gnd 16 25 (exposed pad) 19 22 20 21 24 23 17 8 phase2 lgate2 boot2 ugate2 vout2 v o u t 2 q2 l 2 c 1 1 c 1 7 3 . 3 v r 1 0 c 1 2 v i n 1 0 f 1 0 f 0 . 1 f r 1 1 c 1 4 10 11 9 12 7 bsc119 n03s q4 bsc119 n03s 0 0 c 1 3 4 . 7 h 2 2 0 f q1 l 1 c 2 c 3 r 4 1 0 f 0 . 1 f r 5 c 4 bsc119 n03s q3 bsc119 n03s 0 r b o o t 1 0 c 1 6 . 8 h 2 2 0 f r 8 3 . 9 c 1 0 0 . 1 f 5 v a l w a y s o n 3 . 3 v a l w a y s o n entrip1 entrip2 1 6 fb2 fb1 2 5 1 5 0 k 1 5 0 k c 9 4 . 7 f r 6 1 0 0 k p g o o d i n d i c a t o r c 1 6 4 . 7 f ref 3 c 1 5 0 . 2 2 f tonsel skipsel 4 14 f r e q u e n c y c o n t r o l p w m / d e m / u l t r a s o n i c en on off 13 r 1 4 6 . 5 k r 1 5 1 0 k c 2 1 c 2 0 r 1 2 1 5 k r 1 3 1 0 k c 1 8 c 1 9 0 . 1 f gnd 15 6 v t o 2 5 v v ref 2v enc 18 on off r b o o t 2 r i l i m 1 r i l i m 2
RT8223P 3 ds8223p-01 june 2011 www.richtek.com pin no. pin name pin function 9 boot2 boost flying capacitor connection for smps2. connect to an external capacitor according to the typical application circuits. 10 ugate2 upper gate driver output for smps2. ugate2 swings between phase2 and boot2. 11 phase2 switch node for smps2. phase2 is the internal lower supply rail for the ugate2 high side gate driver. phase2 is also the current-sense input for the smps2. 12 lgate2 lower gate driver output for smps2. lgate2 swings between gnd and vreg5. 13 en master enable input. the ref/vreg5/vreg3 are enabled if it is within logic high level and disabled if it is less than the logic low level. 14 skipsel operation mode selectable input. connect to vreg5 or vreg3 : ultrasonic mode connect to ref : pwm mode connect to gnd : dem mode 16 vin supply input for 5v/3.3v ldo and feed forward on-time circuitry. 17 vreg5 5v linear regulator output. vreg5 is also the supply voltage for the lower gate driver and analog supply voltage for the device. 18 enc smps enable input. pull up to vreg3 or vreg5 to turn on both switch channels. short to gnd to shutdown them. 19 lgate1 lower gate driver output for smps1. lgate1 swings between gnd and vreg5. 20 phase1 switch node for smps1. phase1 is the internal lower supply rail for the ugate1 high side gate driver. phase1 is also the current-sense input for the smps1. 21 ugate1 upper gate driver output for smps1. ugate1 swings between phase1 and boot1. 22 boot1 boost flying capacitor connection for smps1. connect to an external capacitor according to the typical application circuits. 23 pgood power good output for channel 1 and channel 2. (logical and). 24 vout1 bypass pin for smps1. connect to the smps1 output to bypass efficient power for vreg5 pin. vout1 is also for the smps1 output soft-discharge. 15, 25 (exposed pad) gnd ground for smps controller. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8223P 4 ds8223p-01 june 2011 www.richtek.com function block diagram smps2 pwm buck controller boot2 ugate2 phase2 lgate2 gnd vreg5 vout2 fb2 entrip2 pgood smps1 pwm buck controller boot1 ugate1 phase1 lgate1 vreg5 vout1 fb1 entrip1 vreg5 thermal shutdown ref sw5 threshold tonsel skipsel vin vreg5 power-on sequence clear fault latch en vreg3 sw3 threshold ref vreg3 enc vreg5 10a vreg5 10a
RT8223P 5 ds8223p-01 june 2011 www.richtek.com recommended operating conditions (note 4) z supply voltage, v in ------------------------------------------------------------------------------------------ 6v to 25v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vin, en to gnd ----------------------------------------------------------------------------------------------- ? 0.3v to 30v z phasex to gnd dc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to 30v < 20ns ----------------------------------------------------------------------------------------------------------- ? 8v to 38v z bootx to phasex ------------------------------------------------------------------------------------------ ? 0.3v to 6v z entripx, skipsel, tonsel, pgood to gnd ------------------------------------------------------ ? 0.3v to 6v z vreg5, vreg3, fbx, voutx, enc, ref to gnd -------------------------------------------------- ? 0.3v to 6v z ugatex to phasex dc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to (vreg5 + 0.3v) < 20ns ----------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z lgatex to gnd dc ---------------------------------------------------------------------------------------------------------------- ? 0.3v to (vreg5 + 0.3v) < 20ns ----------------------------------------------------------------------------------------------------------- ? 2.5v to 7.5v z power dissipation, p d @ t a = 25 c wqfn-24l 4x4 ------------------------------------------------------------------------------------------------ 1.923w z package thermal resistance (note 2) wqfn-24l 4x4, ja ------------------------------------------------------------------------------------------ 52 c/w wqfn-24l 4x4, jc ------------------------------------------------------------------------------------------ 7 c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z junction temperature ---------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------- 200v
RT8223P 6 ds8223p-01 june 2011 www.richtek.com electrical characteristics to be continued (v in = 12v, v en = v enc = 5v, v entrip1 = v entrip2 = 2v, no load, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit input supply vin standby current i vin_sby v in = 6v to 25v, entripx = gnd -- 200 -- a vin shutdown supply current i vin_shdn v in = 6v to 25v, entripx = en = gnd -- 20 40 a quiescent power consumption p vin +p pvcc both smps on, v fbx = 2.1v, skipsel = gnd, v out1 = 5v, v out2 = 3.3v (note 5) -- 5 7 mw smps output and fb voltage dem mode 1.975 2 2.025 pwm mode (note 6) -- 2 -- fbx voltage v fb x ultrasonic mode -- 2.032 -- v output voltage adjust range v out x smps1, smps2 2 -- 5.5 v v outx discharge current v outx = 0.5v, v entripx = 0v 10 45 -- ma on-time v out1 = 5.05v (200khz) 1895 2105 2315 tonsel = gnd v out2 = 3.33v (250khz) 999 1110 1221 v out1 = 5.05v (300khz) 1227 1403 1579 tonsel = ref v out2 = 3.33v (375khz) 647 740 833 v out1 = 5.05v (400khz) 895 1052 1209 on-time pulse width t on tonsel = reg5 v out2 = 3.33v (500khz) 475 555 635 ns minimum off-time t off v fb x = 1.9v 200 300 400 ns ultrasonic mode frequency skipsel = vreg5 or vreg3 22 33 -- khz soft-start soft-start time t ssx internal soft-start -- 2 -- ms current sense entripx source current i entripx v entripx = 0.9v 9.4 10 10.6 a entripx current temperature coefficient tc ientripx in comparison with 25c (note 6) -- 4700 -- ppm/c entripx adjustment range v entripx = i entripx x r entripx 0.515 -- 3 v current limit threshold gnd ? phasex, v entripx = 2v 180 200 220 mv zero-current threshold gnd ? phasex in dem -- 3 -- mv
RT8223P 7 ds8223p-01 june 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit internal regulator and reference v out1 = gnd, i vreg5 < 100ma 4.8 5 5.2 v out1 = gnd, 6.5v < v in < 25v, i vreg5 < 100ma 4.75 5 5.25 vreg5 output voltage v vreg5 v out1 = gnd, 5.5v < v in < 25v, i vreg5 < 50ma 4.75 5 5.25 v v out2 = gnd, i vreg3 < 100ma 3.2 3.33 3.46 v out2 = gnd, 6.5v < v in < 25v, i vreg3 < 100ma 3.13 3.33 3.5 vreg3 output voltage v vreg3 v out2 = gnd, 5.5v < v in < 25v, i vreg3 < 50ma 3.13 3.33 3.5 v vreg5 output current i vreg5 v vreg5 = 4.5v, v out1 = gnd 100 175 250 ma vreg3 output current i vreg3 v vreg3 = 3v, v out2 = gnd 100 175 250 ma v out1 rising edge 4.6 4.75 4.9 vreg5 switch-over threshold to v out1 v sw5 v out1 falling edge 4.3 4.4 4.5 v v out2 rising edge 2.975 3.125 3.25 vreg3 switch-over threshold to v out2 v sw3 v out2 falling edge 2.775 2.875 2.975 v vregx switch-over equivalent resistance r swx vregx to v outx , 10ma -- 1.5 3 ref output voltage v ref no external load 1.98 2 2.02 v ref load regulation 0 < i load < 100 a -- 10 -- mv ref sink current ref in regulation 5 -- -- a uvlo rising edge -- 4.2 4.45 vreg5 under voltage lockout threshold falling edge 3.7 3.9 4.1 v vreg3 under voltage lockout threshold smpsx off -- 2.5 -- v power good pgood detect, fbx falling edge 82 85 88 pgood threshold hysteresis, rising edge with ss delay time -- 6 -- % pgood propagation delay falling edge, 50mv overdrive -- 10 -- s pgood leakage current high state, forced to 5.5v -- -- 1 a pgood output low voltage i sink = 4ma -- -- 0.3 v fault detection over voltage protection trip threshold v fb_ovp ovp detect, fbx rising edge 109 112 116 % over voltage protection propagation delay fbx = 2.35v -- 5 -- s under voltage protection trip threshold v fb_uvp uvp detect, fbx falling edge 49 52 56 %
RT8223P 8 ds8223p-01 june 2011 www.richtek.com parameter symbol test conditions min typ max unit uvp shutdown blanking time t shdn_uvp from entripx enable -- 5 -- ms thermal shutdown thermal shutdown t shdn -- 150 -- c thermal shutdown hysteresis -- 10 -- c logic input low level (dem mode) -- -- 0.8 ref level (pwm mode) 1.8 -- 2.3 skipsel input voltage high level (ultrasonic mode) 2.7 -- -- v low level (smps off) -- -- 0.25 on level (smps on) 0.515 -- 3 entripx input voltage v entripx high level (smps off) 4.5 -- -- v rising edge -- 0.4 0.515 entripx low level threshold falling edge 0.25 0.36 -- v logic-high v ih 2.4 -- -- en threshold voltage logic-low v il -- -- 0.4 v en voltage v en floating, default enable 2.4 3.3 4.2 v v en = 0.2v, source 1.5 3 5 en current i en v en = 5v, sink -- 3 8 a logic-high v ih_enc 2 -- -- enc threshold voltage logic-low v il_enc -- -- 0.6 v v out1 / v out2 = 200khz/250khz -- -- 0.8 v out1 / v out2 = 300khz/375khz 1.8 -- 2.3 tonsel setting voltage v out1 / v out2 = 400khz/500khz 2.7 -- -- v v tonsel , v skipsel = 0v or 5v ? 1 -- 1 input leakage current v enc = 0v or 5v ? 1 -- 1 a internal boot switch internal boost switch on-resistance vreg5 to bootx, 10ma -- 40 80 power mosfet drivers ugatex, high state, bootx to phasex forced to 5v -- 4 8 ugatex on-resistance ugatex, low state, bootx to phasex forced to 5v -- 1.5 4 lgatex, high state -- 4 8 lgatex on-resistance lgatex, low state -- 1.5 4 lgatex rising -- 30 -- dead time ugatex rising -- 40 -- ns
RT8223P 9 ds8223p-01 june 2011 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. p vin + p vreg5 note 6. guaranteed by design.
RT8223P 10 ds8223p-01 june 2011 www.richtek.com typical operating characteristics vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) 1 dem mode ultrasonic mode pwm mode v in = 20v tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v vout2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) 1 dem mode ultrasonic mode pwm mode v in = 12v tonsel = gnd, en = floating, v entrip1 = 5v, v entrip2 = 1.5v vout2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) 1 dem mode ultrasonic mode pwm mode v in = 20v tonsel = gnd,en = floating, v entrip1 = 5v, v entrip2 = 1.5v vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) 1 dem mode ultrasonic mode pwm mode v in = 8v, tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v vout1 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) 1 dem mode ultrasonic mode pwm mode tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v v in = 12v vout2 efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) 1 dem mode ultrasonic mode pwm mode v in = 8v tonsel = gnd, en = floating, v entrip1 = 5v, v entrip2 = 1.5v
RT8223P 11 ds8223p-01 june 2011 www.richtek.com vout1 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 dem mode ultrasonic mode pwm mode v in = 8v tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v vout1 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 dem mode ultrasonic mode pwm mode v in = 12v tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v vout2 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 dem mode ultrasonic mode pwm mode v in = 8v tonsel = gnd, en = floating, v entrip1 = 5v, v entrip2 = 1.5v vout2 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 dem mode ultrasonic mode pwm mode v in = 12v tonsel = gnd, en = floating, v entrip1 = 5v, v entrip2 = 1.5v vout2 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 dem mode ultrasonic mode pwm mode v in = 20v tonsel = gnd, en = floating, v entrip1 = 5v, v entrip2 = 1.5v vout1 switching frequency vs. load current 0 20 40 60 80 100 120 140 160 180 200 220 0.001 0.01 0.1 1 10 load current (a) switching frequency (khz) 1 dem mode ultrasonic mode pwm mode v in = 20v tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v
RT8223P 12 ds8223p-01 june 2011 www.richtek.com battery current vs. input voltage 0.1 1.0 10.0 100.0 6 7 8 9 10111213141516171819202122232425 input voltage (v) battery current (ma) 1 dem mode ultrasonic mode pwm mode tonsel = gnd, en = floating, v entrip1 = v entrip2 = 0.91v no load reference voltage vs. output current 2.0000 2.0008 2.0016 2.0024 2.0032 2.0040 2.0048 2.0056 2.0064 2.0072 2.0080 -10 0 10 20 30 40 50 60 70 80 90 100 output current (a) reference voltage (v) 1 v in = 12v, tonsel = gnd, en = floating, v entrip1 = v entrip2 = 5v vreg3 output voltage vs. output current 3.330 3.334 3.338 3.342 3.346 3.350 3.354 3.358 0 10203040506070 output current (ma) output voltage (v) 1 v in = 12v, tonsel = gnd, en = floating, v entrip1 = v entrip2 = 5v vreg5 output voltage vs. output current 4.970 4.976 4.982 4.988 4.994 5.000 5.006 0 20406080100 output current (ma) output voltage (v) 1 v in = 12v, tonsel = gnd, en = floating, v entrip1 = v entrip2 = 5v vout1 output voltage vs. load current 5.000 5.006 5.012 5.018 5.024 5.030 5.036 5.042 5.048 5.054 5.060 5.066 5.072 5.078 5.084 5.090 0.001 0.01 0.1 1 10 load current (a) output voltage (v) 1 dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = floating, v entrip1 = 1.5v, v entrip2 = 5v vout2 output voltage vs. load current 3.380 3.386 3.392 3.398 3.404 3.410 3.416 3.422 3.428 3.434 3.440 3.446 0.001 0.01 0.1 1 10 load current (a) output voltage (v) 1 dem mode ultrasonic mode pwm mode v in = 12v, tonsel = gnd, en = floating, v entrip1 = 5v, v entrip2 = 1.5v
RT8223P 13 ds8223p-01 june 2011 www.richtek.com reference voltage vs. temperature 1.984 1.987 1.990 1.993 1.996 1.999 2.002 2.005 2.008 2.011 -50 -25 0 25 50 75 100 125 temperature ( c) reference voltage (v) 1 v in = 12v, v entrip1 = v entrip2 = 5v, en = floating, tonsel = gnd time (400 s/div) ref (2v/div) en (2v/div) en = floating, v entrip1 = v entrip2 = 5v vreg5, vreg3 and ref start up no load, v in = 12v, tonsel = gnd, vreg5 (5v/div) vreg3 (2v/div) standby input current vs. input voltage 240 241 242 243 244 245 246 247 248 249 250 7 8 9 101112131415161718192021222324 input voltage (v) standby input current (a) 1 no load, en = floating, v entrip1 = v entrip2 = 5v shutdown input current vs. input voltage 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 8 9 101112131415161718192021222324 input voltage (v) shutdown input current (a) 1 no load, en = gnd, v entrip1 = v entrip2 = 5v power on from enc time (1ms/div) enc (5v/div) v out1 (5v/div) pgood (5v/div) no load v in = 12v, tonsel = gnd, skipsel = ref, en = floating, v entrip1 = v entrip2 = 1.5v, v enc = 5v v out2 (2v/div) power off from enc time (4ms/div) no load enc (5v/div) v out1 (5v/div) pgood (5v/div) v out2 (2v/div) v in = 12v, tonsel = gnd, skipsel = ref, en = floating, v entrip1 = v entrip2 = 1.5v, v enc = 5v
RT8223P 14 ds8223p-01 june 2011 www.richtek.com vout1 pwm mode load transient response time (20 s/div) ugate1 (20v/div) v out1_ac (50mv/div) lgate1 (5v/div) v in = 12v, tonsel = gnd, inductor current (5a/div) en = floating, skipsel = ref, i out1 = 0a to 6a vout2 pwm mode load transient response time (20 s/div) v out2_ac (50mv/div) lgate2 (5v/div) inductor current (5a/div) en = floating, skipsel = ref, i out2 = 0a to 6a v in = 12v, tonsel = gnd, ugate2 (20v/div) power off from entrip2 time (2ms/div) no load v in = 12v, tonsel = gnd, skipsel = ref, en = floating, v entrip1 = v entrip2 = 1.5v entrip2 (5v/div) v out2 (2v/div) pgood (5v/div) power on from entrip1 time (1ms/div) entrip1 (5v/div) v out1 (2v/div) v in = 12v, tonsel = gnd, skipsel = ref, en = floating, no load v entrip1 = v entrip2 = 1.5v pgood (5v/div) time (2ms/div) power off from entrip1 no load v in = 12v, tonsel = gnd, skipsel = ref, en = floating, v entrip1 = v entrip2 = 1.5v entrip1 (5v/div) v out1 (2v/div) pgood (5v/div) power on from entrip2 time (1ms/div) entrip2 (5v/div) v out2 (2v/div) v in = 12v, tonsel = gnd, skipsel = ref, en = floating, no load v entrip1 = v entrip2 = 1.5v pgood (5v/div)
RT8223P 15 ds8223p-01 june 2011 www.richtek.com ovp time (4ms/div) pgood (5v/div) v out1 (2v/div) no load, v in = 12v, tonsel = gnd, en = floating, skipsel = gnd v out2 (2v/div) uvp time (100 s/div) v out1 (5v/div) v in = 12v, tonsel = gnd, ugate1 (20v/div) lgate1 (5v/div) pgood (5v/div) en = floating, skipsel = ref
RT8223P 16 ds8223p-01 june 2011 www.richtek.com application information the RT8223P is a dual, mach response tm drv tm dual ramp valley mode synchronous buck controller. the controller is designed for low voltage power supplies for notebook computers. richtek's mach response tm technology is specifically designed for providing 100ns ? instant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load-transient timing problems of fixed-frequency current mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a dual output application. the RT8223P includes 5v (vreg5) and 3.3v (vreg3) linear regulators. vreg5 linear regulator can step down the battery voltage to supply both internal circuitry and gate drivers. the synchronous-switch gate drivers are directly powered from vreg5. when vout1 voltage is above 4.75v, an automatic circuit will switch the power of the device from vreg5 linear regulator to vout1. pwm operation the mach response tm drv tm mode controller relies on the output filter capacitor's effective series resistance (esr) to act as a current sense resistor, so the output ripple voltage provides the pwm ramp signal. refer to the RT8223P's function block diagram, the synchronous high side mosfet will be turned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet will be turned off. the pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range. another one shot sets a minimum off-time (300ns typ.). the on-time one shot will be triggered if the error comparator is high, the low side switch current is below the current limit threshold, and the minimum off-time one shot has timed out. / on out in t= k(v v) where ? k ? is set by the tonsel pin connection (table 1). the on-time guaranteed in the electrical characteristics table is influenced by switching delays in the external high side power mosfet. two external factors that influence switching frequency accuracy are resistive drops in the two conduction loops (including inductor and pc board resistance) and the dead time effect. these effects are the largest contributors to the change in frequency with changing load current. the dead-time effect increases the effective on-time by reducing the switching frequency. it occurs only in pwm mode (skipsel= ref) when the inductor current reverses at light or negative load currents. with reversed inductor current, the inductor 's emf causes phasex to go high earlier than normal, thus extending the on-time by a period equal to the low-to-high dead time. for loads above the critical conduction point, the actual switching frequency is : / out drop1 on in drop1 drop2 f = (v v ) (t (v v v )) ++? where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, which includes the synchronous rectifier, inductor, and pc board resistances. v drop2 is the sum of the resistances in the charging path, and t on is the on-time. pwm frequency and on-time control the mach response tm control architecture runs with pseudo constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. the high side switch on-time is inversely proportional to the input voltage as measured by v in , and proportional to the output voltage. there are two benefits of a constant switching frequency. first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band. second, the inductor ripple current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. frequency for the 3v smps is set at 1.25 times higher than the frequency for 5v smps. this is done to prevent audio-frequency ? beating ? between the two sides, which switch asynchronously for each side. the frequencies are set by the tonsel pin connection as shown in table 1. the on-time is given by :
RT8223P 17 ds8223p-01 june 2011 www.richtek.com table 1. tonsel connection and switching frequency tonsel smps 1 k-factor ( s) smps 1 frequency (khz) smps 2 k-factor ( s) smps 2 frequency (khz) approximate k-factor error (%) gnd 5 200 4 250 10 ref 3.33 300 2.67 375 10 vreg5 or vr eg3 2.5 400 2 500 10 operation mode selection (skipsel) the RT8223P supports three operation modes : diode- emulation mode, ultrasonic mode, and forced-ccm mode. user can set operation mode via the skipsel pin. diode-emulation mode (skipsel=gnd) in diode-emulation mode, the RT8223P automatically reduces switching frequency at light-load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly. as the output current decreases from heavy-load condition, the inductor current is also reduced and eventually comes to the point when its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial negative current when the inductor free- wheeling current becomes negative. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next ? on ? cycle. the on-time is kept the same as that in the heavy-load condition. in reverse, when the output current increases from light load to heavy-load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. the transition load point to the light-load operation is shown as follows (figure 1) : figure 1. boundary condition of ccm/dem in out load (skip) on (v v ) it 2l ? ? where t on is the on-time. the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation mode operation. however this is normal and results in high efficiency. trade-offs in pfm noise vs. light load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load transient response (especially at low input-voltage levels). ultrasonic mode (skipsel = vreg5 or vreg3) the RT8223P activates an unique diode-emulation mode with a minimum switching frequency of 25khz, called the ultrasonic mode. the ultrasonic mode avoids audio- frequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. in ultrasonic mode, the high side switch gate driver signal is or with an internal oscillator (>25khz). once the internal oscillator is triggered, the controller enters constant off-time control. when output voltage reaches the setting peak threshold, the controller turns on the low side mosfet until the controller detects that the inductor current dropped has below the zero-crossing threshold. the internal timer provides a constant off-time control and it is effective to regulate the output voltage under light load conditions. i l t 0 t on slope = (v in -v out ) / l i l, peak i load = i l, peak / 2
RT8223P 18 ds8223p-01 june 2011 www.richtek.com forced ccm mode (skipsel = ref) the low noise, forced ccm mode (skipsel = ref) disables the zero-crossing comparator, which controls the low side switch on-time. this causes the low side gate- driver waveform to become the complement of the high side gate-driver waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio of v out /v in . the benefit of forced ccm mode is to keep the switching frequency fairly constant, but it comes at a cost. the no load battery current can be from 10ma to 40ma, depending on the external mosfets. reference and linear regulators (ref, vregx) the 2v reference (ref) is accurate within 1% over the entire operating temperature range, making ref useful as a precision system reference. bypass ref to gnd with a minimum 0.22 f ceramic capacitor. ref can supply up to 100 a for external loads. loading ref reduces the voutx output voltage slightly because of the reference load-regulation error. the RT8223P includes 5v (vreg5) and 3.3v (vreg3) linear regulators. the vreg5 regulator supplies a total of 100ma for internal and external loads, including the mosfet gate driver and pwm controller. the vreg3 regulator supplies up to 100ma for external loads. bypass vreg5 and vreg3 with a minimum 4.7 f ceramic capacitor. when the 5v main output voltage is above the vreg5 switch over threshold (4.75v), an internal 1.5 p-channel mosfet switch connects vout1 to vreg5, while simultaneously shutting down the vreg5 linear regulator. similarly, when the 3.3v main output voltage is above the vreg3 switch over threshold (3.125v), an internal 1.5 p-channel mosfet switch connects vout2 to vreg3, while simultaneously shutting down the vreg3 linear regulator. it can decrease the power dissipation from the same battery, because the converted efficiency of smps is better than the converted efficiency of the linear regulator. current-limit setting (entripx) the RT8223P has a cycle-by-cycle current-limit control. the current-limit circuit employs an unique ? valley ? current sensing algorithm. if the magnitude of the current sense signal at phasex is above the current-limit threshold, the pwm is not allowed to initiate a new cycle (figure 2). the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are functions of the sense resistance, inductor value, and battery and output voltage. figure 2. ? valley ? current-limit the RT8223P uses the on-resistance of the synchronous rectifier as the current-sense element and supports temperature compensated mosfet r ds(on) sensing. the r ilimx resistor between the entrip x pin and gnd sets the current-limit threshold. the resistor r ilimx is connected to a current source from entripx , which is 10 a typically at room temperature. the current source has a 4700ppm/ c temperature slope to compensate the temperature dependency of the r ds(on) . when the voltage drop across the sense resistor or low side mosfet equals 1/10 the voltage across the r ilimx resistor, positive current limit will be activated. the high side mosfet will not be turned on until the voltage drop across the mosfet falls below 1/10 the voltage across the r ilimx resistor. choose a current limit resistor by following equations v ilimx = (r ilimx x10 a)/10 = i ilimx x r ds(on) r ilimx = (i ilimx x r ds(on) ) x 10/10 a carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signal at phasex and gnd. mount or place the ic close to the low side mosfet. mosfet gate driver (ugatex, lgatex) the high side driver is designed to drive high-current, low r ds(on) n-mosfet(s). when configured as a floating driver, a 5v bias voltage is delivered from the vreg5 supply. i l t 0 i l, peak i lim i load
RT8223P 19 ds8223p-01 june 2011 www.richtek.com the average drive current is calculated by the gate charge at v gs = 5v times the switching frequency. the instantaneous drive current is supplied by the flying capacitor between the bootx and phasex pins. a dead time to prevent shoot through is internally generated between high side mosfet off to the low side mosfet on, and the low side mosfet off to the high side mosfet on. the low side driver is designed to drive high current, low r ds(on) n-mosfet(s). the internal pull-down transist or that drives lgate x low is robust, with a 1.5 typical on- resistance. a 5v bias voltage is delivered from the vreg5 supply. the instantaneous drive current is supplied by an input capacitor connected between vreg5 and gnd. for high current applications, some combinations of high and low side mosfets might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency killing, emi-producing shoot-through currents. this can be remedied by adding a resistor in series with bootx, which increases the turn-on time of the high side mosfet without degrading the turn-off time (figure 3). figure 3. increasing the ugatex rise time soft-start the RT8223P provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. the soft-start (ss) automatically begins once the chip is enabled. during soft- start, it clamps the ramping of internal reference voltage which is compared with fbx signal. the typical soft- start duration is 2 ms. a unique pwm duty limit control that prevents output over voltage during soft-start period is designed specifically for fbx floating. uvlo protection the RT8223P features vreg5 under voltage lockout protection (uvlo). when the vreg5 voltage is lower than 3.9v (typ.) and the vreg3 voltage is lower than 2.5v (typ.), both switch power supplies are shut off. this is non-latch protection. power good output (pgood) pgood is an open-drain type output and requires a pull- up resistor. pgood is actively held low in soft-start, standby, and shutdown. it is released when both output voltages are above 91% of the nominal regulation point. the pgood goes low if either output turns off or is 15% below its nominal regulator point. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage. if the output voltage exceeds 12% of its set voltage threshold, the over voltage protection is triggered and the lgatex low side gate drivers are forced high. this activates the low side mosfet switch, which rapidly discharges the output capacitor and pulls the input voltage downward. the RT8223P is latched once ovp is triggered and can only be released by toggling en, entripx or cycling v in . there is a 5 s delay built into the over voltage protection circuit to prevent false alarm. note that the lgatex latching high causes the output voltage to dip slightly negative when energy has been previously stored in the lc tank circuit. for loads that cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse polarity clamp. if the over-voltage condition is caused by a short in the high side switch, completely turning on the low side mosfet can create an electrical short between the battery and gnd, which will blow the fuse and disconnect the battery from the output. output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. if the output is less than 52% of its set voltage threshold, under voltage protection will be triggered, and then both ugatex and lgatex gate drivers will be forced low. the uvp will be ignored for at least 5ms (typ.) after start-up or a rising edge on entripx. toggle bootx ugatex phasex r boot v in
RT8223P 20 ds8223p-01 june 2011 www.richtek.com entripx or cycle v in to reset the uvp fault latch and restart the controller. thermal protection the RT8223P features thermal shutdown protection to prevent overheat damage to the device. thermal shutdown occurs when the die temperature exceeds 150 c. all internal circuitry is inactive during thermal shutdown. the RT8223P triggers thermal shutdown if vregx is not supplied from voutx, while the input voltage on v in and the drawing current from vregx are too high. even if vregx is supplied from voutx, large power dissipation on automatic switches caused by overloading vregx, may also result in thermal shutdown. discharge mode (soft-discharge) when entripx is low and a transition to standby or shutdown mode occurs, or the output under voltage fault latch is set, the output discharge mode will be triggered. during discharge mode, the output capacitors' residual charge will be discharged to gnd through an internal switch. table 2. operation mode truth table mode condition comment power up vregx < uvlo threshold transitions to discharge mode after a vin por and after ref becomes valid. vreg5, vreg3, and ref remain active. run en = high, vout1 or vout2 enabled normal operation. over voltage pr otection either output > 111% of the nominal level. lgatex is forced high. vreg3, vreg5 and ref active. exited by vin por or by toggling en, entripx, enc under voltage pr otection either out put < 52% of the nominal level after 3ms time-out expires and output is enabled both ugatex and lgatex are forced low and enter discharge mode. vreg3, vreg5 and ref are active. exited by vin por or by toggling en, entripx, enc discharge either smps output is still high in either standby mode or shutdown mode during discharge mode, there is one path to discharge the outputs capacitor residual charge. that is output capacitor discharge to gnd through an internal switch. standby entrip x < startup threshold, en = high. vreg3, vreg5 and ref are active. shutdown en = low all circuitry off. thermal shutdown t j > 150c all circuitry off. exit by vin por or by toggling en, entripx, enc shutdown mode the RT8223P smps1, smps2, vreg3 and vreg5 have independent enabling controls. drive en, entrip1 and entrip2 below the precise input falling-edge trip level to place the RT8223P in its low power shutdown state. the RT8223P consumes only 20 a of input current while in shutdown. when shutdown mode is activated, the reference turns off. the accurate 0.4v falling-edge threshold on the en pin can be used to detect a specific analog voltage level as well as to shutdown the device. once in shutdown, the 2.4v rising-edge threshold activates, providing sufficient hysteresis for most applications. power up sequencing and on/off controls (enc) entrip1 and entrip2 control the smps power up sequencing. when the RT8223P is in single channel mode, entrip1 or entrip2 enables the respective output when entripx voltage descends below 3v. furthermore, the RT8223P can also be in dual channel mode. in this mode, outputs are enabled when enc voltage rises above 2v.
RT8223P 21 ds8223p-01 june 2011 www.richtek.com table 3. power up sequencing en (v) enc (v) entrip1 entrip2 ref vreg 5 vreg 3 smps1 smps2 low low x x off off off off off ?>2.4v? => high low x x on on on off off ?>2.4v? => high ?>2v ? => high off off on on on off off ?>2.4v? => high ?>2v ? => high off on on on on off on ?>2.4v? => high ?>2v ? => high on off on on on on off ?>2.4v? => high ?>2v ? => high on on on on on on on output voltage setting (fbx) connect a resistor voltage-divider at the fbx pin between voutx and gnd to adjust the respective output voltage between 2v and 5.5v (figure 4). referring to figure 4 as an example, choose r2 to be approximately 10k , and solve for r1 using the equation : outx fbx r1 vv1 r2 ?? ?? =+ ?? ?? ?? ?? where v fbx is 2v. figure 4. setting v outx with a resistor voltage divider output inductor selection the switching frequency (on-time) and operating point (% ripple or lir) determine the inductor value as shown in the following equation : () on in outx load(max) tvv l lir i ? = where lir is the ratio of the peak to peak ripple current to the average inductor current. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ) : peak load(max) load(max) ii (lir/2)i ?? =+ ?? the calculation above shall serve as a general reference. to further improve the transient response, the output inductance can be reduced even further. this needs to be considered along with the selection of the output capacitor. output capacitor selection the capacitor value and esr determine the amount of output voltage ripple and load transient response. thus, the capacitor value must be greater than the largest value calculated from below equations : () 2 outx load off(min) in sag in outx out outx off(min) in v (i ) l k t v v vv 2c v k t v ?+ = ?? ?? ? ? ?? ?? ?? ?? 2 2 load soar out outx (i ) l v cv ? = phasex lgatex r1 r2 v outx v in ugatex voutx fbx
RT8223P 22 ds8223p-01 june 2011 www.richtek.com p p load(max) out 1 v lir i esr 8c f ? ?? = + ?? ?? where v sag and v soar are the allowable amount of undershoot voltage the and overshoot voltage in load transient, v p-p is the output ripple voltage, t off(min) is the minimum off-time, and k is a factor listed in table 1. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8223P, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn- 24l 4x4 packages, the thermal resistance, ja , is 52 c/ w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for wqfn-24l 4x4 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8223P package, the derating curve in figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 5. derating curve for the RT8223P package layout considerations layout is very important in high frequency switching converter designs, the pcb could radiate excessive noise and contribute to the converter instability with improper layout. certain points must be considered before starting a layout using the RT8223P. ` place the filter capacitor close to the ic, within 12mm (0.5 inch) if possible. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching nodes. ` connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. use 0.65mm (25mils) or wider trace. ` all sensitive analog traces and components such as voutx, fbx, gnd, entripx, pgood, and tonsel should be placed away from high voltage switching nodes such as phasex, lgatex, ugatex, or bootx nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` place the ground terminal of vin capacitor(s), voutx capacitor(s), and source of low side mosfets as close as possible. the pcb trace defined as phase x node, which connects to source of high side mosfet, drain of low side mosfet and high voltage side of the inductor, should be as short and wide as possible. 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8223P 23 ds8223p-01 june 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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